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lt3015 1 3015f typical application features description 1.5a, low noise, negative linear regulator with precision current limit the lt ? 3015 is a low noise, low dropout, negative linear regulator with fast transient response. the device supplies up to 1.5a of output current at a typical dropout voltage of 310mv. operating quiescent current is typically 1.1ma and drops to < 1a in shutdown. quiescent current is also well controlled in dropout. in addition to fast transient response, the lt3015 exhibits very low output noise, making it ideal for noise sensitive applications. the lt3015 regulator is stable with a minimum 10f output capacitor. moreover, the regulator can use small ceramic capacitors without the necessary addition of esr as is common with other regulators. internal protection circuitry includes reverse output protection, precision current limit with foldback and thermal limit with hysteresis. the lt3015 is available as an adjustable device with a C1.22v reference voltage. packages include the 5-lead to-220 and dd-pak, a thermally enhanced 12-lead msop and the low profile (0.75 mm) 8-lead 3mm 3mm dfn. C5v, C1.5a, low-noise regulator applications n output current: 1.5a n dropout voltage: 310mv n precision current limit with foldback n low output noise: 60v rms (10hz to 100khz) n low quiescent current: 1.1ma n precision positive or negative shutdown logic n fast transient response n wide input voltage range: C1.8v to C30v n adjustable output voltage range: C1.22v to C29.5v n controlled quiescent current in dropout n < 1a quiescent current in shutdown n stable with 10f output capacitor n stable with ceramic, tantalum or aluminum capacitors n thermal limit with hysteresis n reverse output protection n 5-lead to-220 and dd-pak, thermally enhanced 12-lead msop and 8-lead 3mm 3mm 0.75mm dfn packages n post-regulator for switching supplies n negative logic supplies n low noise instrumentation n industrial supplies n negative complement to the lt1963a l , lt, ltc, ltm, thinsot, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. gnd adj out shdn in lt3015 10f 10f 3.40k 1% 10.5k 1% v out C5v C1.5a v in C5.5v to C30v 3015 ta01 dropout voltage load current (a) 0 0 dropout voltage (mv) 400 350 300 250 200 150 100 50 450 C0.8 C1.0 C1.2 C1.4 C1.6 C0.2 C0.4 3015 ta01a C0.6 t j = 25c dd-pak/to-220 dfn/msop
lt3015 2 3015f pin configuration absolute maximum ratings in pin voltage .........................................................33v out pin voltage (note 10) ......................................33v out to in differential voltage (note 10) ........C0.3v, 33v adj pin voltage (with respect to in pin) (note 10) .............C0.3v, 33v shdn pin voltage (with respect to in pin) (note 10) .............C0.3v, 55v shdn pin voltage (with respect to gnd pin) ..........................C33v, 22v (note 1) top view dd package 8-lead (3mm s 3mm) plastic dfn 5 6 7 8 9 in 4 3 2 1in in shdn gnd out out adj gnd t jmax = 125c, ja = 40c/w, jc = 7.5c/w exposed pad (pin 9) is in, must be soldered to pcb 1 2 3 4 5 6 in in in in shdn gnd 12 11 10 9 8 7 out out out out adj gnd top view mse package 12-lead plastic msop 13 in t jmax = 125c, ja = 37c/w, jc = 10c/w exposed pad (pin 13) is in, must be soldered to pcb q package 5-lead plastic dd-pak front view tab is in out adj in gnd shdn 5 4 3 2 1 t jmax = 125c, ja = 14c/w, jc = 3c/w t package 5-lead plastic to-220 out adj in gnd shdn front view 5 4 3 2 1 tab is in t jmax = 125c, ja = 50c/w, jc = 3c/w output short-circuit duration .......................... indefinite operating junction temperature range (note 9) e-, i-grade ........................................ C40c to 125c mp-grade ......................................... C55c to 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10sec) ms12e package ................................................ 300c q, t packages ................................................... 250c
lt3015 3 3015f order information lead free finish tape and reel part marking* package description temperature range lt3015edd#pbf lt3015edd#trpbf lfxs 8-lead (3mm 3mm) plastic dfn C40c to 125c lt3015idd#pbf lt3015idd#trpbf lfxs 8-lead (3mm 3mm) plastic dfn C40c to 125c lt3015emse#pbf lt3015emse#trpbf 3015 12-lead plastic msop C40c to 125c lt3015imse#pbf lt3015imse#trpbf 3015 12-lead plastic msop C40c to 125c lt3015mpmse#pbf lt3015mpmse#trpbf 3015 12-lead plastic msop C55c to 125c LT3015EQ#pbf LT3015EQ#trpbf lt3015q 5-lead plastic dd-pak C40c to 125c lt3015iq#pbf lt3015iq#trpbf lt3015q 5-lead plastic dd-pak C40c to 125c lt3015mpq#pbf lt3015mpq#trpbf lt3015q 5-lead plastic dd-pak C55c to 125c lt3015et#pbf lt3015et#trpbf lt3015t 5-lead plastic to-220 C40c to 125c lt3015it#pbf lt3015it#trpbf lt3015t 5-lead plastic to-220 C40c to 125c lead based finish tape and reel part marking* package description temperature range lt3015edd lt3015edd#tr lfxs 8-lead (3mm 3mm) plastic dfn C40c to 125c lt3015idd lt3015idd#tr lfxs 8-lead (3mm 3mm) plastic dfn C40c to 125c lt3015emse lt3015emse#tr 3015 12-lead plastic msop C40c to 125c lt3015imse lt3015imse#tr 3015 12-lead plastic msop C40c to 125c lt3015mpmse lt3015mpmse#tr 3015 12-lead plastic msop C55c to 125c LT3015EQ LT3015EQ#tr lt3015q 5-lead plastic dd-pak C40c to 125c lt3015iq lt3015iq#tr lt3015q 5-lead plastic dd-pak C40c to 125c lt3015mpq lt3015mpq#tr lt3015q 5-lead plastic dd-pak C55c to 125c lt3015et lt3015et#tr lt3015t 5-lead plastic to-220 C40c to 125c lt3015it lt3015it#tr lt3015t 5-lead plastic to-220 C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ electrical characteristics parameter conditions min typ max units minimum in pin voltage (note 11) i load = C0.5a i load = C1.5a l C1.75 C1.8 C2.3 v adj pin voltage (notes 2, 3) v in = C2.3v, i load = C1ma C30v < v in < C2.3v, C1.5a < i load < C1ma l C1.208 C1.196 C1.22 C1.22 C1.232 C1.244 v v line regulation (note 2) v in = C2.3v to C30v, i load = C1ma l 2.5 6 mv load regulation (note 2) v in = C2.3v, i load = C1ma to C1.5a v in = C2.3v, i load = C1ma to C1.5a l 23.8 9 mv mv the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c.
lt3015 4 3015f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. the lt3015 is tested and specified for these conditions with the adj pin connected to the out pin. note 3. maximum junction temperature limits operating conditions. the regulated output voltage specification does not apply for all possible combinations of input voltage and output current. if operating at maximum output current, limit the input voltage range. if operating at maximum input voltage, limit the output current range. note 4. to satisfy minimum input voltage requirements, the lt3015 is tested and specified for these conditions with an external resistor divider (54.9k top, 49.9k bottom) for an output voltage of C2.56v. the external resistor adds 25a of dc load on the output. note 5. dropout voltage is the minimum input-to-output voltage differential needed to maintain regulation at a specified output current. in dropout, the output voltage is: v in + v dropout . electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. parameter conditions min typ max units dropout voltage v in = v out(nominal) (notes 4, 5) i load = C1ma i load = C1ma i load = C100ma i load = C100ma i load = C500ma (dfn/msop) i load = C500ma (dfn/msop) i load = C500ma (dd-pak/to-220) i load = C500ma (dd-pak/to-220) i load = C1.5a (dfn/msop) i load = C1.5a (dfn/msop) i load = C1.5a (dd-pak/to-220) i load = C1.5a (dd-pak/to-220) l l l l l l 0.055 0.1 0.17 0.2 0.31 0.41 0.095 0.16 0.16 0.24 0.23 0.32 0.27 0.39 0.39 0.5 0.51 0.68 v v v v v v v v v v v v gnd pin current v in = v out(nominal) (notes 4, 6) i load = 0ma i load = C1ma i load = C100ma i load = C500ma i load = C1.5a l l l l l 1.1 1.15 2.9 9.5 35 2.4 2.5 7.0 23 70 ma ma ma ma ma output voltage noise c out = 10f, i load = C1.5a, bw = 10hz to 100khz 60 v rms adj pin bias current (notes 2, 7) v in = C2.3v C200 30 200 na shutdown threshold (note 11) v out = off-to-on (positive) v out = off-to-on (negative) v out = on-to-off (positive) v out = on-to-off (negative) l l l l 1.07 C1.34 0.5 1.21 C1.20 0.73 C0.73 1.35 C1.06 C0.5 v v v v shdn pin current (note 8) v shdn = 0v v shdn = 15v v shdn = C15v l l l C1.0 0 17 C2.8 10 27 C4.5 a a a quiescent current in shutdown v in = C6v, shdn = 0v l 0.01 6 a ripple rejection v in - v out = C1.5v (avg), v ripple = 0.5v p-p f ripple = 120hz, i load = C1.5a 55 65 db current limit v in = C2.3v, v out = 0v v in = C2.3v, v out = 0.1v l l 1.8 1.75 2.0 1.95 2.2 2.15 a a input reverse leakage current v in = 30v, v out , v adj , v shdn = open circuit l 1.55 1.7 ma note 6. gnd pin current is tested with v in = v out(nominal) and a current source load. therefore, the device is tested while operating in dropout. this is the worst-case gnd pin current. gnd pin current decreases slightly at higher input voltages. note 7. positive adj pin bias current flows into the adj pin. note 8. positive shdn pin current flows into the shdn pin. note 9. the lt3015 is tested and specified under pulsed load conditions such that t j ? t a . the lt3015e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating temperature range are assured by design, characterization, and correlation with statistical process controls. the lt3015i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3015mp is 100% tested and guaranteed over the full C55c to 125c operating junction temperature range. note 10. parasitic diodes exist internally between the out, adj, shdn pins and the in pin. do not drive the out, adj, and shdn pins more that 0.3v below the in pin during fault conditions, and these pins must remain at a voltage more positive than in during normal operation. note 11. the shdn threshold must be met to ensure device operation.
lt3015 5 3015f typical performance characteristics typical dropout voltage (dd-pak/to-220) guaranteed dropout voltage (dd-pak/to-220) dropout voltage (dd-pak/to-220) quiescent current lt3015 adj pin voltage lt3015 output voltage typical dropout voltage (dfn/msop) guaranteed dropout voltage (dfn/msop) dropout voltage (dfn/msop) t a = 25c, unless otherwise noted. output current (a) 0 0 dropout voltage (mv) 400 350 300 250 200 150 100 50 450 C0.8 C1 C1.2 C1.4 C1.6 C0.2 C0.4 3015 g01 C0.6 C55c C40c 25c 125c output current (a) 0 0 dropout voltage (mv) 500 400 300 200 100 600 C0.8 C1 C1.2 C1.4 C1.6 C0.2 C0.4 3015 g02 C0.6 t j 25c t j 125c = test points temperature (c) C75 0 dropout voltage (mv) 400 450 300 350 200 250 100 150 50 500 75 100 125 150 175 0C25C50 25 3015 g03 50 i l = C1.5a i l = C0.5a i l = C0.1a i l = C1ma output current (a) 0 0 dropout voltage (mv) 400 500 300 200 100 600 C0.8 C1 C1.2 C1.4 C1.6 C0.2 C0.4 3015 g04 C0.6 C55c C40c 25c 125c output current (a) 0 0 dropout voltage (mv) 500 600 700 400 300 200 100 800 C0.8 C1 C1.2 C1.4 C1.6 C0.2 C0.4 3015 g05 C0.6 = test points t j 25c t j 125c temperature (c) C75 0 dropout voltage (mv) 400 300 200 100 600 500 75 100 125 150 175 0C25C50 25 3015 g06 50 i l = C1.5a i l = C0.5a i l = C0.1a i l = C1ma temperature (c) C75 0 quiescent current (ma) C1 C0.8 C0.6 C0.4 C0.2 C1.4 C1.2 75 100 125 150 175 0C25C50 25 3015 g07 50 v shdn = v in v in = C6v r l = 120k, i l = C10a v out = C1.22v v shdn = 0v temperature (c) C75 C1.192 adj pin voltage (v) C1.226 C1.232 C1.220 C1.214 C1.208 C1.202 C1.196 C1.244 C1.238 75 100 125 150 175 0C25C50 25 3015 g08 50 v in = C2.3v i l = C1ma temperature (c) C75 C4.900 output voltage (v) C5.050 C5.075 C5.025 C5.000 C4.975 C4.950 C4.925 C5.100 75 100 125 150 175 0C25C50 25 3015 g09 50 v in = C5.5v i l = C1ma v out = C5v
lt3015 6 3015f typical performance characteristics lt3015 gnd pin current gnd pin current vs i load positive shdn pin thresholds negative shdn pin thresholds shdn pin input current shdn pin input current lt3015 quiescent current lt3015 quiescent current lt3015 gnd pin current t a = 25c, unless otherwise noted. input voltage (v) 0 0 quiescent current (ma) C1.0 C0.8 C0.6 C0.4 C0.2 C1.2 C6 C7 C8 C9 C10 C3C2C1 C4 3015 g10 C5 v shdn = v in t j = 25c v out = C1.22v r l = 121k v shdn = 0v input voltage (v) 0 0 quiescent current (ma) C1.0 C0.8 C0.6 C0.4 C0.2 C1.2 C6 C7 C8 C9 C10 C3C2C1 C4 3015 g10 C5 v shdn = v in t j = 25c v out = C5v r l = 499k v shdn = 0v input voltage (v) 0 0 gnd pin current (ma) C20 C15 C10 C5 C25 C6 C7 C8 C9 C10 C3C2C1 C4 3015 g12 C5 r l = 1.2k i l = C1ma* r l = 2.4 i l = C0.5a* r l = 0.81 i l = C1.5a* r l = 12 i l = C0.1a* t j = 25c v shdn = v in *for v out = C1.22v input voltage (v) 0 0 gnd pin current (ma) 35 30 25 20 15 5 10 40 C6 C7 C8 C9 C10 C3C2C1 C4 3015 g13 C5 r l = 5k i l = C1ma* r l = 10 i l = C0.5a* r l = 3.3 i l = C1.5a* r l = 50 i l = C0.1a* t j = 25c v shdn = v in *for v out = C5v t j = C55c t j = C40c t j = 25c t j = 125c output current (a) 0.0 0 gnd pin current (ma) C30 C25 C20 C15 C10 C5 C35 C0.8 C1.0 C1.2 C1.4 C1.6 C0.2 C0.4 3015 g14 C0.6 v in = C2.3v v out = C1.22v temperature (c) C75 0.0 positive shdn pin threshold (v) 1.2 1.0 0.8 0.6 0.2 0.4 1.4 75 100 125 150 175 0C25C50 25 3015 g15 50 v in = C2.3v turn on threshold turn off threshold temperature (c) C75 0 negative shdn pin threshold (v) C1.2 C1.0 C0.8 C0.6 C0.4 C0.2 C1.4 75 100 125 150 175 0C25C50 25 3015 g16 50 turn off threshold turn on threshold v in = C2.3v shdn pin voltage (v) C30 C10 shdn pin current (a) 20 15 10 5 0 C5 25 5 10152025 C15C20C25 C10 C5 3015 g17 0 C55c 25c 125c v in = C30v positive current flows into the pin temperature (c) C75 C6 shdn pin current (a) 15 18 21 12 9 3 6 0 C3 24 75 100 125 150 175 C25C50 0 25 3015 g18 50 v in = C15v positive current flows into the pin v shdn = C15v v shdn = 15v
lt3015 7 3015f typical performance characteristics load regulation current limit vs v in Cv out current limit vs temperature adj pin bias current adj pin bias current line regulation t a = 25c, unless otherwise noted. temperature (c) C75 C200 adj pin bias current (na) 150 100 50 C50 0 C100 C150 200 75 100 125 150 175 C25C50 0 25 3015 g19 50 v in = C2.3v positive current flows into the pin input voltage (v) 0 20 adj pin bias current (na) 70 50 60 40 30 80 C18 C21 C24 C27 C30 C6C3 C9 C12 3015 g20 C15 t j = 25c positive current flows into the pin temperature (c) C75 0.0 line regulation (mv) C2.0 C3.0 C4.0 C5.0 C6.0 C7.0 C8.0 C9.0 C1.0 C10.0 75 100 125 150 175 C25C50 0 25 3015 g21 50 v in = C5.5v to C30v v out = C5v v in = C2.3v to C30v v out = C1.22v i l = C1ma temperature (c) C75 C32 load regulation (mv) C24 C20 C16 C12 C8 C4 C28 0 75 100 125 150 175 C25C50 0 25 3015 g22 50 v out = C1.22v v out = C5v v in = v out(nominal) C1v i l = C1ma to C1.5a input/output differential (v) 0 0.0 current limit (a) C0.4 C0.6 C0.8 C1.0 C1.2 C1.4 C1.6 C1.8 C2.0 C0.2 C2.2 C20 C25 C30 C10C5 C15 3015 g26 v out = 0v C55c 25c 125c temperature (c) C75 0.0 current limit (a) C0.4 C0.6 C0.8 C1.0 C1.2 C1.4 C1.6 C1.8 C2.0 C0.2 C2.2 75 100 125 150 175 C25C50 0 25 3015 g27 50 v in = C2.3v v out = 0v lt3015 input ripple rejection lt3015 input ripple rejection ripple rejection vs temperature frequency (hz) 10 0 ripple rejection (db) 20 10 30 40 50 60 70 10m 100 1k 10k 100k 1m 3015 g28 t j = 25c i l = C1.5a v out = C1.22v v in = C2.7v c out = 47f c out = 10f frequency (hz) 10 0 ripple rejection (db) 20 10 30 40 50 60 70 10m 100 1k 10k 100k 1m 3015 g29 t j = 25c i l = C1.5a v out = C5v v in = C6.5v + v rms ripple c out = 10f, c ff = 0 c out = 10f, c ff = 10nf c out = 47f, c ff = 10nf temperature (c) C75 0 ripple rejection (db) 10 20 30 40 50 60 70 75 100 125 150 175 C25C50 0 25 3015 g30 50 i l = C1.5a v out = C1.22v v in = C2.7v + 0.5v p-p ripple at f = 120hz
lt3015 8 3015f typical performance characteristics minimum input voltage output noise spectral density rms output noise vs load current rms output noise vs feedforward capacitor (c ff ) lt3015 10hz to 100khz output noise lt3015 10hz to 100khz output noise, c ff = 0 t a = 25c, unless otherwise noted. lt3015 10hz to 100khz output noise, c ff = 10nf temperature (c) C75 0 minimum input voltage (v) C1.0 C0.8 C0.6 C0.4 C0.2 C1.2 C1.4 C1.6 C1.8 C2.0 C2.2 75 100 125 150 175 C25C50 0 25 3015 g31 50 i l = C1ma v shdn = v in i l = C1.5a frequency (hz) 10 100 1k 10k 0.1 output noise spectral density (v/ hz) 1 10 100k 3015 g32 v shdn = v in c out = 10f i l = C1.5a i fb-divider = 100a v out = C5v c ff = 10nf v out = C1.22v v out = C5v c ff = 0 t j = 25c load current (a) C1m C10m C100m 0 output noise (v rms ) 175 150 125 100 75 50 25 250 225 200 C1 3015 g33 c out = 10f i fb-divider = 100a t j = 25c f = 10hz to 100khz v out = C5v, c ff = 0 v out = C5v, c ff = 120pf v out = C5v, c ff = 1nf v out = C1.22v v out = C5v, c ff = 10nf feedforward capacitance, c ff (f) 10p 100p 1n 10n 100n 0 25 50 75 100 output noise (v rms ) 125 150 175 200 225 250 1 3015 g34 i l = C1.5a c out = 10f f = 10hz to 100khz i fb-divider = 100a t j = 25c v out = C5v v out = C1.22v v out 100v/div c out = 10f v out = C1.22v i l = C1.5a 3015 g35 1ms/div v out 200v/div c out = 10f v out = C5v i l = C1.5a c ff = 0 3015 g36 1ms/div v out 200v/div c out = 10f v out = C5v i l = C1.5a c ff = 10nf 3015 g37 1ms/div shdn transient response, i l = C5ma, c ff = 0 shdn transient response, i l = C1.5a, c ff = 0 v shdn 1v/div v out 2v/div r l = 1k c out = 10f v out = C5v c ff = 0 3015 g23 25ms/div v shdn 1v/div v out 2v/div r l = 3.3 c out = 10f v out = C5v c ff = 0 3015 g24 250s/div
lt3015 9 3015f typical performance characteristics lt3015 transient response, c out = 47f lt3015 transient response, c ff = 0, c out = 10f lt3015 transient response, c ff = 10nf, c out = 10f lt3015 transient response, c ff = 10nf, c out = 47f start-up time vs c ff lt3015 transient response, c out = 10f t a = 25c, unless otherwise noted. feedforward capacitor, c ff (f) 100p 1n 10n 0.001 0.01 0.1 1.0 10 start-up time (ms) 100 100n 3015 g38 i l = C1.5a i fb-divider = 100a t j = 25c v out = C1.22v v out = C5v v out = C3v v out = C12v v out = C15v v out 100mv/div i out 1a/div c out = 10f v out = C1.22v i out = C50ma to C1.5a 3015 g39 25s/div v out 100mv/div i out 1a/div c out = 47f v out = C1.22v i out = C50ma to C1.5a 3015 g40 25s/div v out 100mv/div i out 1a/div c out = 10f v out = C5v c ff = 0 i fb-divider = 100a i out = C50ma to C1.5a 3015 g41 25s/div v out 100mv/div i out 1a/div c out = 10f v out = C5v c ff = 10nf i fb-divider = 100a i out = C50ma to C1.5a 3015 g42 25s/div v out 100mv/div i out 1a/div c out = 47f v out = C5v c ff = 10nf i fb-divider = 100a i out = C50ma to C1.5a 3015 g43 25s/div shdn transient response, i l = C1.5a, c ff = 10nf v shdn 1v/div v out 2v/div r l = 3.3 c out = 10f v out = C5v c ff = 10nf 3015 g25 250s/div
lt3015 10 3015f pin functions in (pins 1, 2, exposed pad pin 9 / 1, 2, 3, 4, exposed pad pin 13 / 3, tab / 3, tab ): input. these pins supply power to the regulator. the tab of the dd-pak, to-220 and the exposed backside pad of the dfn and msop packages is an electrical connection to in and to the devices sub- strate. for proper electrical and thermal performance, tie all in pins together and tie in to the exposed backside or tab of the relevant package on the pcb. see the applica- tions information section for thermal considerations and calculating junction temperature. the lt3015 requires a bypass capacitor at in. in general, a batterys output impedance rises with frequency, so include a bypass ca- pacitor in battery powered applications. an input bypass capacitor in the range of 1f to 10f generally suffices, but applications with large load transients may require higher input capacitance to prevent input supply droop and prevent the regulator from entering dropout. shdn (pin 3 / 5 / 1 / 1): shutdown. use the shdn pin to put the lt3015 into a micropower shutdown state. the shdn function is bi-directional, allowing use of either positive or negative logic. the shdn pin threshold voltages are referenced to gnd. the output of the lt3015 is off if the shdn pin is pulled within 0.73v of gnd. driving the shdn pin more than 1.21v turns the lt3015 on. drive the shdn pin with either a logic gate or with open collector/drain logic using a pull-up resistor. the resistor supplies the pull-up current of the open collector/drain gate, typically several microamperes. the typical shdn pin current is 2.8a out of the pin (for negative logic) or 17a into the pin (for positive logic). if the shdn func- tion is unused, connect the shdn pin to v in to turn the device on. if the shdn pin is floated, then the lt3015 is off. a parasitic diode exists between shdn and in of the lt3015. therefore, do not drive the shdn pin more than 0.3v below in during normal operation or during a fault condition. the shdn pin can also be used to set a programmable undervoltage lockout (uvlo) threshold for the regulator input supply. gnd (pins 4, 5 / 6, 7 / 2 / 2): ground. tie all gnd pin(s) together and tie the bottom of the output voltage setting resistor divider directly to the gnd pin(s) for optimum load regulation performance. adj (pin 6 / 8 / 4 / 4): adjust. this pin is the error ampli- fiers non-inverting input. it has a typical bias current of 30na that flows into the pin. the adj pin reference voltage is C1.22v referred to gnd, and the output voltage range is C1.22v to C29.5v. a parasitic substrate diode exists between adj and in of the lt3015. therefore, do not drive adj more than 0.3v below in during normal operation or during a fault condition. out (pins 7, 8 / 9, 10, 11, 12 / 5 / 5): output. these pins supply power to the load. tie all out pins together for best performance. use a minimum output capacitor of 10f to prevent oscillations. large load transient applications require larger output capacitors to limit peak voltage tran- sients. see the applications information section for more information on output capacitance. a parasitic substrate diode exists between out and in of the lt3015. therefore, do not drive out more than 0.3v below in during normal operation or during a fault condition. (dfn/msop/q/t)
lt3015 11 3015f block diagram C1.20v 1.21v v ref + C adj in shdn i limit foldback out npn driver bias circuitry adj pin bias current compensation qpower 3015 bd v th r sns + _ + C C + error amp C + i limit amp gnd the lt3015 regulator is a 1.5a negative low dropout linear regulator featuring precision current limit and precision bi-directional shutdown. the device supplies up to 1.5a of output load current at a typical dropout voltage of 310mv. moreover, the low 1.1ma operating quiescent current drops to less than 1a in shutdown. in addition to low quiescent current, the lt3015 incorporates several protection features that make it ideal for battery powered applications. in dual supply applications where the regu- lators load is returned to a positive supply, out can be pulled above gnd by 30v and still allow the lt3015 to start up and operate. adjustable operation the lt3015 regulator has an output voltage range of C1.22v to C29.5v. output voltage is set by the ratio of two external resistors as shown in figure 1. the device regulates the output to maintain the adj pin voltage to C1.22v referred to ground. the current in r1 equals C1.22v/r1 and the current in r2 equals the current in r1 plus the adj pin bias current. the adj pin bias current, 30na at 25c, flows into the adj pin. calculate the output voltage using the formula shown in figure 1. the value of r1 should be less than 50k to minimize errors in the output voltage created by the adj pin bias current. note that in shutdown, the output is off and the divider current is zero. curves of applications information adj pin voltage vs temperature, adj pin bias current vs temperature and adj pin bias current vs input voltage appear in the typical performance characteristics section. the adjustable device is tested and specified with the adj pin tied to the out pin for a C1.22v output voltage. specifications for output voltages greater than C1.22v are proportional to the ratio of the desired v out to C1.22v (v out /C1.22v). for example, load regulation for an out- put current change of C1ma to C1.5a is typically 2mv at v out = C1.22v. at v out = C5v, load regulation equals: (C5v/C1.22v) ? (2mv) = 8.2mv gnd lt3015 adj out shdn in v out c in v in r1 r2 c out 3015 f01 figure 1. adjustable operation v out = C1.22v 1 + r2 r1 ? ? ? ? ? ? + i adj () r2 () v adj = C1.22v and i adj = 30na at 25 c output range = C1.22 to C 29.5v
lt3015 12 3015f applications information table 1 shows 1% resistor divider values for some com- mon output voltages with a resistor divider current of approximately 100a. table 1. output voltage resistor divider values v out (v) r1 (k) r2 (k) C2.5 12.1 12.7 C3.0 12.1 17.8 C3.3 12.1 20.5 C5.0 12.1 37.4 C12.0 12.1 107 C15.0 12.4 140 feedforward capacitance: output voltage noise, transient performance, and psrr the lt3015 regulators provide low output voltage noise over the 10hz to 100khz bandwidth while operating at full load current. output voltage noise is approximately 240nv/ hz over this frequency while operating in unity-gain configuration. for higher output voltages (using a resistor divider), the output voltage noise gains up accordingly. to lower the output voltage noise for higher output voltages, include a feedforward capacitor (c ff ) from v out to v adj . a good quality, low leakage, capacitor is recommended. this capacitor bypasses the resistor divider network at high frequencies; and hence, reduces the output noise. with the use of a 10nf feedforward capacitor, the output noise decreases from 220v rms to 70v rms when the output voltage is set to C5v by a 100a feedback resistor divider. higher values of output voltage noise are often measured if care is not exercised with regard to circuit layout and testing. crosstalk from nearby traces induces unwanted noise onto the lt3015s output. moreover, power supply ripple rejection (psrr) must also be considered, as the lt3015 does not exhibit unlimited psrr; and thus, a small portion of the input noise propagates to the output. using a feedforward capacitor (c ff ) from v out to v adj has the added benefit of improving transient response and psrr for output voltages greater than C1.22v. with no feedforward capacitor, the response and settling times will increase as the output voltage is raised above C1.22v. use the equa- tion in figure 2 to determine the minimum value of c ff to achieve a transient (and noise) performance that is similar to C1.22v output voltage performance regardless of the chosen output voltage (see transient response and output noise in the typical performance characteristics section). it is important to note that the start-up time is affected by the use of a feedforward capacitor. start-up time is directly proportional to the size of the feedforward capacitor and the output voltage, and is inversely proportional to the feedback resistor divider current. in particular, it slows to 860s with a 10nf feedforward capacitor and a 10f output capacitor for an output voltage set to C5v by a 100a feedback resistor divider current. gnd lt3015 adj out shdn in v out c in v in r1 r2 c out c ff 3015 f02 c ff ?o'?"t* fb-divider i fb-divider = v out /(r1+r2) figure 2. feedforward capacitor for fast transient response, low noise, and high psrr output capacitance and transient performance the lt3015 regulator is stable with a wide range of output capacitors. the esr of the output capacitor affects stabil- ity, most notably with small capacitors. use a minimum output capacitor of 10f with an esr of 500m or less to prevent oscillations. the lt3015s load transient response is a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide im- proved transient response for larger load current changes. extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are specified with eia temperature char- acteristic codes of z5u, y5v, x5r, and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coefficients as shown in figures 3 and 4. when used with a 5v regulator, a 16v 10f y5v capacitor
lt3015 13 3015f voltage and temperature coefficients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric microphone works. for a ceramic capacitor, the stress can be induced by vibra- tions in the system or thermal transients. the resulting voltages produced can cause appreciable amounts of noise. a ceramic capacitor produced the trace in figure 5 in response to light tapping from a pencil. similar vibration induced behavior can masquerade as increased output voltage noise. applications information can exhibit an effective value as low as 1f to 2f for the dc bias voltage applied and over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across tem- perature, while the x5r is less expensive and is available in higher values. care still must be exercised when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be significant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified in situ for all applications. v out 1mv/div v out = C1.3v c out = 10f i l = 10a 3015 f05 1ms/div figure 5. noise resulting from tapping on a ceramic capacitor dc bias voltage (v) both capacitors are 16v, 1210 case size, 10f 0 C100 change in value (%) C80 642 8 10 12 3015 f03 14 0 20 C60 C40 x5r y5v C20 16 figure 3. ceramic capacitor dc bias characteristics temperature (c) C50 C100 change in value (%) C80 250C25 50 75 100 3015 f04 0 20 40 C60 C40 y5v C20 125 both capacitors are 16v, 1210 case size, 10f x5r figure 4. ceramic capacitor temperature characteristics overload recovery like many ic power regulators, the lt3015 has safe oper- ating area protection. the safe operating area protection activates at in-to-out differential voltages greater than 8v. the safe area protection decreases current limit as the in-to-out differential voltage increases and keeps the power transistor inside a safe operating region for all values of forward input-to-output voltage up to the lt3015s absolute maximum ratings. when power is first applied and input voltage rises, the output follows the input and keeps the in-to-out differential voltage small, allowing the regulator to supply large output currents and start-up into high current loads. with a high input voltage, a problem can occur wherein removal of an output short does not allow the output voltage to fully recover. other ltc negative linear regulators such as the lt1175 and lt1964 also exhibit this phenomenon, so it is not unique to the lt3015.
lt3015 14 3015f applications information the problem occurs with a heavy output load when input voltage is high and output voltage is low. such situations occur easily after the removal of a short-circuit or if the shutdown pin is pulled high after the input voltage has already been turned on. the load line for such a load intersects the output current curve at two points. if this happens, the regulator has two stable output operating points. with this double intersection, the input power supply may need to be cycled down to zero and brought up again to make the output recover. shutdown/uvlo the shdn pin is used to put the lt3015 into a micro power shutdown state. the lt3015 has an accurate C1.20v threshold (during turn-on) on the shdn pin. this threshold can be used in conjunction with a resistor divider from the system input supply to define an accurate undervoltage lockout (uvlo) threshold for the regulator. the shdn pin current (at the threshold) needs to be considered when determining the resistor divider network. thermal considerations the lt3015s maximum rated junction temperature of 125c limits its power handling capability. two components comprise the power dissipated by the device: 1. output current multiplied by the input-to-output dif- ferential voltage: i out ? (v in - v out ) and 2. gnd pin current multiplied by the input voltage: i gnd ? v in determine gnd pin current using the gnd pin current curves in the typical performance characteristics sec- tion. total power dissipation is the sum of the above two components. the lt3015 regulator incorporates a thermal shutdown circuit designed to protect the device during overload conditions. the typical thermal shutdown temperature is 165c and the circuit incorporates about 8c of hyster- esis. for continuous normal conditions, do not exceed the maximum junction temperature rating of 125c. carefully consider all sources of thermal resistance from junction to ambient, including other heat sources mounted in close proximity to the lt3015. the undersides of the dfn and msop packages have ex- posed metal from the lead frame to the die attachment. both packages allow heat to directly transfer from the die junction to the printed circuit board metal to control maximum operating junction temperature. the dual-in-line pin arrangement allows metal to extend beyond the ends of the package on the topside (component side) of the pcb. connect this metal to in on the pcb. the multiple in and out pins of the lt3015 also assist in spreading heat to the pcb. for surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through-holes can also be used to spread the heat gener- ated by power devices. tables 2-4 list thermal resistance as a function of copper area in a fixed board size. all measurements were taken in still air on a 4 layer fr-4 board with 1oz solid internal planes and 2oz top/bottom external trace planes with a total board thickness of 1.6mm. the four layers were electrically isolated with no thermal vias present. pcb layers, copper weight, board layout and thermal vias will affect the resul- tant thermal resistance. for more information on thermal resistance and high thermal conductivity test boards, refer to jedec standard jesd51, notably jesd51-12 and jesd51-7. achieving low thermal resistance necessitates attention to detail and careful pcb layout.
lt3015 15 3015f table 2. measured thermal resistance for dfn package copper area board area thermal resistance (junction-to-ambient) top side* backside 2500mm 2 2500mm 2 2500mm 2 40c/w 1000mm 2 2500mm 2 2500mm 2 40c/w 225mm 2 2500mm 2 2500mm 2 41c/w 100mm 2 2500mm 2 2500mm 2 42c/w *device is mounted on topside table 3. measured thermal resistance for msop package copper area board area thermal resistance (junction-to-ambient) top side* backside 2500mm 2 2500mm 2 2500mm 2 37c/w 1000mm 2 2500mm 2 2500mm 2 37c/w 225mm 2 2500mm 2 2500mm 2 38c/w 100mm 2 2500mm 2 2500mm 2 40c/w *device is mounted on topside table 4. measured thermal resistance for dd-pak package copper area board area thermal resistance (junction-to-ambient) top side* backside 2500mm 2 2500mm 2 2500mm 2 14c/w 1000mm 2 2500mm 2 2500mm 2 16c/w 225mm 2 2500mm 2 2500mm 2 19c/w *device is mounted on topside t package, 5-lead to-220 thermal resistance (junction-to-case) = 3c/w calculating junction temperature example: given an output voltage of C2.5v, an input voltage range of C3.3v 5%, an output current range of 1ma to 500ma, and a maximum ambient temperature of 85c, what is the maximum junction temperature? the power dissipated by the lt3015 equals: i out(max) ? (v in(max) - v out ) + i gnd ? (v in(max) ) where: i out(max) = C500ma v in(max) = C3.465v i gnd at (i out = C500ma, v in = C3.465v) = C6.5ma applications information thus: p = C500ma(C3.465v + 2.5v) + C6.5ma ? (C3.465v) = 0.505w using a dfn package, the thermal resistance is in the range of 40c/w to 42c/w depending on the copper area. therefore, the junction temperature rise above ambient approximately equals: 0.505w ? 41c/w = 20.7c the maximum junction temperature equals the maxi- mum ambient temperature plus the maximum junction temperature rise above ambient or: t jmax = 85c + 20.7c = 105.7c protection features the lt3015 incorporates several protection features that make it ideal for use in battery-powered applications. in addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device protects itself against reverse input voltages and reverse output voltages. precision current limit and thermal overload protections are intended to protect the lt3015 against current over- load conditions at the output of the device. for normal operation, do not allow the the junction temperature to exceed 125c. pulling the lt3015s output above ground induces no damage to the part. if in is left open circuit or grounded, out can be pulled above gnd by 30v. in addition, out acts like an open circuit, i.e. no current flows into the pin. if in is powered by a voltage source, out sinks the lt3105s short-circuit current and protects itself by thermal limiting. in this case, grounding the shdn pin turns off the device and stops out from sinking the short-circuit current.
lt3015 16 3015f typical applications adjustable current sink gnd lt3015 adj out shdn in v in < C2.3v r1 2k lt1004-1.2 r2 82.5k r4 0.01 r3 2k c1 10f r8 100k c2 10f r7 475 c3 1f 1 4 3 2 8 r5 2.2k c4 3.3f note: adjust r3 for 0 to C1.5a constant current 3015 ta04 r load r6 2.2k C + 1/2 lt1350 package description dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50 bsc 0.70 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc
lt3015 17 3015f package description mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev d) msop (mse12) 0910 rev d 0.53 t 0.152 (.021 t .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 C?0.38 (.009 C .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail b 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0s C 6s typ detail a detail a gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 t 0.102 (.112 t .004) 2.845 t 0.102 (.112 t .004) 4.039 t 0.102 (.159 t .004) (note 3) 1.651 t 0.102 (.065 t .004) 0.1016 t 0.0508 (.004 t .002) 123456 3.00 t 0.102 (.118 t .004) (note 4) 0.406 t 0.076 (.016 t .003) ref 4.90 t 0.152 (.193 t .006) detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 t 0.127 (.035 t .005) 0.42 t 0.038 (.0165 t .0015) typ 0.65 (.0256) bsc
lt3015 18 3015f package description q(dd5) 0610 rev e .028 C .038 (0.711 C 0.965) typ .143 +.012 C.020 3.632 +0.305 C0.508 .067 (1.702) bsc .013 C .023 (0.330 C 0.584) .095 C .115 (2.413 C 2.921) .004 +.008 C.004 0.102 +0.203 C0.102 .050 p .012 (1.270 p 0.305) .059 (1.499) typ .045 C .055 (1.143 C 1.397) .165 C .180 (4.191 C 4.572) .330 C .370 (8.382 C 9.398) .060 (1.524) typ .390 C .415 (9.906 C 10.541) 15 o typ .420 .350 .585 .090 .042 .067 recommended solder pad layout .325 .205 .080 .585 .090 recommended solder pad layout for thicker solder paste applications .042 .067 .420 .276 .320 note: 1. dimensions in inch/(millimeter) 2. drawing not to scale .300 (7.620) .075 (1.905) .183 (4.648) .060 (1.524) .060 (1.524) .256 (6.502) bottom view of dd pak hatched area is solder plated copper heat sink q package 5-lead plastic dd pak (reference ltc dwg # 05-08-1461 rev e)
lt3015 19 3015f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description t package 5-lead plastic to-220 (standard) (reference ltc dwg # 05-08-1421) t5 (to-220) 0801 .028 C .038 (0.711 C 0.965) .067 (1.70) .135 C .165 (3.429 C 4.191) .700 C .728 (17.78 C 18.491) .045 C .055 (1.143 C 1.397) .095 C .115 (2.413 C 2.921) .013 C .023 (0.330 C 0.584) .620 (15.75) typ .155 C .195* (3.937 C 4.953) .152 C .202 (3.861 C 5.131) .260 C .320 (6.60 C 8.13) .165 C .180 (4.191 C 4.572) .147 C .155 (3.734 C 3.937) dia .390 C .415 (9.906 C 10.541) .330 C .370 (8.382 C 9.398) .460 C .500 (11.684 C 12.700) .570 C .620 (14.478 C 15.748) .230 C .270 (5.842 C 6.858) bsc seating plane * measured at the seating plane
lt3015 20 3015f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0611 ? printed in usa related parts typical application part number description comments lt1185 3a, negative linear regulator 670mv dropout voltage, v in = C4.3v to C35v, dd-pak and to-220 packages lt1175 500ma, negative low dropout micropower regulator 500mv dropout voltage, v in = C4.5v to C20v, s8, n8, sot-223, dd-pak and to-220 packages lt1964 200ma, negative low noise low dropout regulator 340mv dropout voltage, low noise: 30v rms , v in = C1.9v to C20v, 3mm 3mm dfn and thinsot packages lt1764a 3a, fast transient response, low noise ldo regulator 340mv dropout voltage, low noise: 40v rms , v in = 2.7v to 20v, to-220 and dd-pak packages, a version stable also with ceramic caps lt1763 500ma, low noise, ldo regulator 300mv dropout voltage, low noise : 20v rms , v in = 1.6v to 20v, stable with 3.3f output capacitors, s8 and 3mm 4mm dfn packages lt1963a 1.5a low noise, fast transient response ldo regulator 340mv dropout voltage, low noise: 40v rms , v in = 2.5v to 20v, a version stable with ceramic caps, to-220, dd-pak, sot-223 and so-8 packages lt1965 1.1a, low noise, ldo regulator 310mv dropout voltage, low noise: 40v rms , v in : 1.8v to 20v, v out : 1.2v to 19.5v, stable with ceramic caps, to-220, dd-pak, msop-8e and 3mm 3mm dfn packages lt3022 1a, low voltage, very low dropout v ldo linear regulator v in = 0.9v to 10v, dropout voltage: 145mv typical, adjustable output (v ref = v out(min) = 200mv), fixed output voltages: 1.2v, 1.5v, 1.8v, stable with low esr, ceramic output capacitors 16-pin 3mm 5mm dfn and msop-16e packages lt3080/lt3080-1 1.1a, parallelable, low noise, low dropout linear regulator 300mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic caps, to-220, dd-pak, sot-223, msop-8e and 3mm 3mm dfn packages; C1 version has integrated internal ballast resistor lt3085 500ma, parallelable, low noise, low dropout linear regulator 275mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic caps, msop-8e and 2mm 3mm dfn packages lt3015 shdn in adj gnd lt3015 shdn in adj out gnd r1 0.01 r2 0.01 r3 2.2k r4 2.2k v out C5v C3.0a r5 50k c3 0.01f v in < C5.5v 8 4 2 3 1 + C 1/2 lt1366 3015 ta03 r9 12.1k 1% r8 37.4k 1% r7 12.1k 1% r6 37.4k 1% out c2 22f c1 22f paralleling regulators for higher output current

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